INFLUENCE OF ARCH SUPPORT INSOLE ON PEOPLE WITH FLATFOOT DURING UPHILL AND DOWNHILL WALKING

The purpose of this study was to investigate the effect of the arch support insole for people with flatfoot during uphill and downhill walking. Sixteen healthy collegiate students with flatfoot were recruited in this study. The heart rate, V02max, and median frequency of surface EMG were recorded and analyzed in this study. Non-parametric Wilcoxon signed-rank test was used for statistics. The derived main results were outlined as follows: (a) V02max had significantly decreased in arch support insole compare to flat foot insole during uphill and downhill walking; (b) arch support insole could reduce the fatigue of rectus femoris muscle during downhill walking which might be associated with the decreased V02max. The integrated research results could effectively be applied to the measurement of muscle fatigue

EFFECT OF SHORT MEDIALSIDE STUDS OM FOOT BIOMECHANICS IN COLLEGIATE SOCCER PLAYERS

The purpose of this study was to examine the effect of modified stud on ankle and foot kinematics, ground reaction force and forefoot force and pressure during sidestep cut (SC) and change direction (CD) movement 6 male collegiate soccer players wore original and medial-side 2mm cut stud shoes and performed SC and CD on the artificial grass. Non-parametric Wilcoxon signed-rank test was used to compare difference between the original and modified studs. The modified stud of non-dominant leg show less inversion than the original stud in SC and CD. The modified stud of non-dominant leg show more force peak form and pressure and that of nondominant legs show more pressure an the original stud during SC and CD. The short medial-side studs with 2mm length can decrease the force inversion of the nondmiiant leg during SC and CD movement and increase the force production of the lower extremities in recreational soccer players

A 23μW Solar-Powered Keyword-Spotting ASIC with Ring-Oscillator-Based Time-Domain Feature Extraction

Voice-controlled interfaces on acoustic Internet-of-Things (IoT) sensor nodes and mobile devices require integrated low-power always-on wake-up functions such as Voice Activity Detection (VAD) and Keyword Spotting (KWS) to ensure longer battery life. Most VAD and KWS ICs focused on reducing the power of the feature extractor (FEx) as it is the most power-hungry building block. A serial Fast Fourier Transform (FFT)-based KWS chip [1] achieved 510nW; however, it suffered from a high 64ms latency and was limited to detection of only 1-to-4 keywords (2-to-5 classes). Although the analog FEx [2]–[3] for VAD/KWS reported 0.2μW-to-1 μW and 10ms-to-100ms latency, neither demonstrated >5 classes in keyword detection. In addition, their voltage-domain implementations cannot benefit from process scaling because the low supply voltage reduces signal swing; and the degradation of intrinsic gain forces transistors to have larger lengths and poor linearity

Design of Sub-10-μW Sub-0.1% THD Sinusoidal Current Generator IC for Bio-Impedance Sensing

This article presents a low-power, low-distortion, and compact mixed-signal sinusoidal current generator (CG) IC for bio-impedance (Bio-Z) sensing applications. By utilizing the digital ΔΣ modulation to bridge the digitally synthesized sinewave data and the analog-domain voltage output, implementation of a low-distortion sinewave lookup table (LUT) is significantly simplified. Not only does this approach lead to the reduced number of routing wires, pin allocation, and output registers after logic synthesis but also, it allows the use of dynamic element matching (DEM) with a low-cost, before interfacing with the digital-to-analog converter (DAC). In addition, 0.5 V of low-supply voltage exploits a highly power-efficient operation for both synthesized digital logic and its subsequent analog circuit chain. To suppress the noise-floor increase that is induced from the reset signal of capacitor-DAC, a half-period reset scheme is introduced. The prototype chip is fabricated in 65-nm CMOS technology and it outputs 2 μAPP of amplitude with 20 kHz of sinusoidal frequency. It records the first sinusoidal CG IC that achieves sub- 10 μW ( 6.2 μW ) of power consumption and sub-0.1% (0.088%) of total harmonic distortion (THD) at the same time which has not been demonstrated ever in the prior arts. Furthermore, 0.059 mm 2 of its compact area facilitates the low-cost production of Bio-Z sensor systems

FlashMAC: A Time-Frequency Hybrid MAC Architecture With Variable Latency-Aware Scheduling for TinyML Systems

With the widespread of deep neural networks (DNNs) in diverse applications, tiny platforms such as Internet-of-Things devices are starting to adopt DNNs. Due to their extreme energy and form factor constraints, conventional digital-only implementations of multiply-and-accumulate (MAC) acceleration faced fundamental limitations. To that end, the investigation into mixed-signal computing architectures is growing rapidly. Motivated by the flash ADC, this article proposes FlashMAC architecture that can natively support multibit multiplication. In addition, through fusing time- and frequency-domain computing methods without power-hungry oscillators, it enables low latency accumulation with low power consumption. As a result, the proposed time-frequency hybrid architecture achieves high energy efficiency with the support for complex DNN models requiring higher precision. To enhance the robustness of PVT variation of the mixed-signal architecture, a frequency calibration loop is integrated. In addition, motivated by the data-dependent performance of the FlashMAC architecture, variable latency-aware scheduling is proposed. The FlashMAC does not skip MAC operations as zero-skipping architectures do, but the latency of the operation can be lower when operands are smaller in magnitude. Tackling the issue through software and hardware co-optimization, loose synchronization architecture and magnitude-aware weight reordering increase the DNN benchmark performance by achieving higher utilization of the parallel FlashMAC array. The proposed features are integrated into a test chip which is fabricated in 65-nm logic CMOS technology. The silicon chip achieves 56.52 TOPS/W peak energy efficiency and a peak operating frequency of 90 MHz. Tested with the VGG16 benchmark trained on the Imagenet dataset, it achieved 17.04-ms latency while showing 11.15 TOPS/W energy efficiency. As a result, compared to the previous state-of-the-art, the proposed FlashMAC achieved 3.15 × higher normalized energy efficiency